Elijah Gaohan Ye

Santa Clara,CA,US

Wenzhou,Zhejiang,China

`$cat my_info`

Hi! 👋

My name is Elijah Gaohan Ye. Elijah is my English first name, and Gaohan is my Chinese first name. I am a hardware engineer working on design-for-test (DFT), design verification, and computer architecture. I earned my Master of Science in Electrical and Computer Engineering from the University of Illinois Urbana-Champaign in May 2026 (GPA 3.86/4.00), and my Bachelor of Science in Computer Engineering from the same institution in December 2023 (GPA 3.96/4.00).

While at UIUC, I was a Teaching Assistant for Digital Systems Laboratory (ECE 385) and Computer System Engineering (ECE 391).

`$cat my_experience`

Most recently, I was a DFT Engineer Intern at Astera Labs on the Leo CXL Memory Controller. I inserted memory BIST and repair across 186 SRAM macros, debugged ATPG, MBIST, and boundary-scan gate-level simulation failures, and built Python toolchains that automate die-to-package remapping of BSDL and STIL test patterns.

Before that, I spent two internships at Rivian Automotive as a Design Verification Intern on the RAP1 Silicon Team, where I developed system-level testcases for RAP1 (Rivian Autonomy Processor), a custom 5nm AI inference chip delivering 1600 sparse TOPS for autonomous driving compute. I enhanced verification coverage, developed system-level and FuSa tests, and worked with UVM testbenches.

My research focuses on computer architecture, particularly hardware-software co-design for accelerating Large Language Models (LLMs), advised by Prof. Nam Sung Kim. I have published work on “Exploiting Intel Advanced Matrix Extensions (AMX) for LLM Inference” in IEEE Computer Architecture Letters (CAL) 2024, which received the IEEE Best Paper Award, and co-authored “ReScue: Reliable and secure CXL memory” at HPCA 2026. My work on transparent memory management for large-scale LLM training and tuning is currently under review.

`$cat my_skills`

Programming: SystemVerilog (Advanced), C/C++ (Advanced), UVM/OVM, Python, Tcl, Bash, CUDA

Hardware Design: RTL Design, CPU Architecture, RISC-V, x86, CXL/PCIe, Cache Design

DFT: ATPG, Boundary Scan (JTAG/BSDL), MBIST, STIL Patterns, Gate-Level Simulation

Physical Design: Custom CMOS Layout, Standard Cell Design, DRC/LVS Verification

Tools: Synopsys TestMAX ATPG, VCS, Verdi, Design Compiler, Cadence Virtuoso, Innovus, Git, Linux, Slurm

`$cat my_interests`

Beyond my interests in computer architecture, DFT, and LLM acceleration, I enjoy playing basketball and working out to stay active and maintain a healthy work-life balance.

news

Jun 1, 2026	Started my internship at Astera Labs as a DFT Engineer Intern on the Leo CXL Memory Controller.
May 15, 2026	🎓 Graduated with a Master of Science in Electrical and Computer Engineering from University of Illinois Urbana-Champaign!
Jan 31, 2026	📄 Our paper “ReScue: Reliable and secure CXL memory” appears at the IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2026.
Dec 11, 2025	Rivian Announces Autonomy & AI Day - RAP1 Processor Unveiled!
Aug 15, 2025	Successfully completed my second internship as Design Verification Intern at Rivian Automotive, achieving over 90% verification coverage and reducing test failure rates significantly.

selected publications

HPCA

ReScue: Reliable and secure CXL memory

Chihun Song, Austin Antony Cruz, Michael Jaemin Kim, Minbok Wi, Gaohan Ye, Kyungsan Kim, Sangyeol Lee, Jung Ho Ahn, and Nam Sung Kim

In IEEE International Symposium on High-Performance Computer Architecture (HPCA), Jan 2026

Abs
CAL

Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference

Hyungyo Kim, Gaohan Ye, Nachuan Wang, Amir Yazdanbakhsh, and Nam Sung Kim

IEEE Computer Architecture Letters, May 2024

Abs HTML PDF

The ever-increasing number of parameters in Large Language Models (LLMs) demands many expensive GPUs for both inference and training. This is because even such a high-end GPU such as NVIDIA A100 can store only a subset of parameters due to its limited memory capacity. To reduce the number of required GPUs, especially for inference, we may exploit the large memory capacity of (host) CPU to store not only all the model parameters but also intermediate outputs which also require a substantial memory capacity. However, this necessitates frequent data transfers between CPU and GPU over the slow PCIe interface, creating a bottleneck that hinders the accomplishment of both low latency and high throughput in inference. To address such a challenge, we first propose CPU-GPU cooperative computing that exploits the Advanced Matrix Extensions (AMX) capability of the latest Intel CPU, codenamed Sapphire Rapids (SPR). Second, we propose an adaptive model partitioning policy that determines the layers of a given LLM to be run on CPU and GPU, respectively, based on their memory capacity requirement and arithmetic intensity. As CPU executes the layers with large memory capacity but low arithmetic intensity, the amount of data transferred through the PCIe interface is significantly reduced, thereby improving the LLM inference performance. Our evaluation demonstrates that CPU-GPU cooperative computing, based on this policy, delivers 12.1x lower latency and 2.2x higher throughput than GPU-only computing for OPT-30B inference when both CPU-GPU and GPU-only computing store the model in CPU memory.