cv

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Basics

Name Gaohan Ye
Label Graduate Student in Electrical and Computer Engineering
Email elijah.gaohan.ye@gmail.com
Phone 510-520-7207
Url https://elijah-ye.github.io
Summary Graduate student at University of Illinois Urbana-Champaign with expertise in computer architecture, hardware design verification, and LLM acceleration. Published researcher with industry experience at Rivian Automotive.

Work

  • 2025.05 - 2025.08
    Design Verification Intern, Special Project
    Rivian Automotive
    Enhanced design verification processes and system-level testing for automotive systems.
    • Increased design verification coverage to over 90% via a new, more efficient coverage generation flow
    • Enhanced an existing integration test suite, reducing the failure rate from over 40% to less than 5%
    • Developed a new system-level test to validate memory access, creating a baseline for future verification tests
    • Authored new FuSa tests to validate error injection and interrupt mechanisms for critical components
  • 2025.01 - Present
    Teaching Assistant for Digital Systems Laboratory, ECE 385
    University of Illinois at Urbana-Champaign
    Teaching assistant for digital systems laboratory course covering FPGA and microprocessor implementations.
    • Evaluated SystemVerilog/FPGA projects and microprocessor system implementations
    • Conducted technical demonstrations and assessments of digital circuits, state machines, and SoC designs
    • Graded lab reports covering combinational/sequential logic, timing analysis, and hardware-software co-design
  • 2024.04 - 2024.08
    Design Verification Intern, Special Project
    Rivian Automotive
    Developed verification infrastructure and performance monitoring for automotive chip designs.
    • Created performance monitor to track AXI transaction signals to test read and write operation performance
    • Increased toggle coverage of chip blocks by creating and implementing new targeted tests
    • Conducted system level verification for the DUT using a custom UVM testbench
    • Developed and executed detailed test plans, identifying bugs and successfully debugging and resolving issues

Education

  • 2024.01 - 2026.05

    Urbana, IL
    Master of Science
    University of Illinois Urbana-Champaign
    Electrical and Computer Engineering
    • Computer Architecture
    • SoC/Hardware Design
    • Network Protocol
    • Operating System
  • 2020.08 - 2023.12

    Urbana, IL
    Bachelor of Science
    University of Illinois Urbana-Champaign
    Computer Engineering
    • Data Structure
    • Algorithm
    • Computer Architecture
    • Operating System

Awards

Publications

  • 2025.01.01
    CXL Memory Device Characterization
    In Progress
    Evaluated Samsung CMM-H CXL memory prototype using Intel MLC benchmarking tools and compared performance characteristics against internal lab CXL SSD implementations.
  • 2024.01.01
    Exploiting Intel Advanced Matrix Extensions (AMX) for LLM Inference
    IEEE Computer Architecture Letters (CAL)
    Contributed to research on Intel Extension for PyTorch utilizing Intel Sapphire Rapids CPU with AMX. Developed CPU-GPU heterogeneous computing techniques to accelerate Large Language Model inference. Collaborated with Prof. Nam Sung Kim's research group to advance computational efficiency and speed. Received IEEE Best Paper Award.

Skills

Programming
System Verilog (Advanced)
C/C++ (Advanced)
UVM/OVM
Python
CUDA
Hardware Design
RTL Design
CPU Architecture
RISC-V
x86
CXL/PCIe
Cache Design
Technologies/Tools
Verdi
VCS
Git
Linux
Intel Extension for PyTorch
Performance Analysis

Languages

English
Native speaker
Chinese
Native speaker

Interests

Computer Architecture
Hardware-Software Co-design
LLM Acceleration
Performance Optimization
Sports & Recreation
Basketball
Workout

Projects

  • 2023.09 - 2023.12
    Multi-stage RISC-V Processor
    Designed and implemented RV32I processor in SystemVerilog with data & branch hazard detection as team project.
    • Achieved 28.6% frequency increase and 47% cache stall reduction
    • Secured 3rd place among 30 groups
    • Implemented complete 5-stage pipeline with hazard detection